HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 231

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): These bits set the synchronous
DRAM write-precharge delay time. This designates the time between the end of a write cycle and
the next bank-active command. This is valid only when synchronous DRAM is connected. After
the write cycle, the next bank-active command is not issued for the period TPC + TRWL.
Bit 11: TRWL1
0
1
Bits 9 and 8—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When DRAM
interface is selected as connected memory, the TRAS bits set the RAS assertion period for CAS-
before-RAS refreshes. When pseudo-SRAM interface is selected, they set the OE/RFSH assertion
period for auto-refreshes. When synchronous DRAM interface is selected, no bank-active
command is issued during the period TPC + TRAS after an auto-refresh command.
In the SH7708, set the same values in the TRAS bits in MCR and DCR.
Bit 9: TRAS1
0
1
Bit 7—Reserved: This bit always reads 0. The write value should always be 0.
Bit 6—Burst Enable (BE): Specifies whether to conduct a burst access of DRAM or pseudo-
SRAM. When accessing synchronous DRAM, burst access is always carried out, regardless of this
bit’s designation.
Bit 6: BE
0
1
Bit 10: TRWL0
0
1
0
1
Bit 8: TRAS0
0
1
0
1
Description
Burst disabled
With DRAM interface, high-speed page mode access
With pseudo-SRAM interface, continuous data transfer in static column
mode
Description
1 cycle
2 cycles
3 cycles
Reserved (cannot be set)
Description
2 cycles
3 cycles
4 cycles
5 cycles
(Initial value)
(Initial value)
(Initial value)
211