DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 772

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 27 Electrical Characteristics
Item
SCI
A/D
converter
WDT
Note:
Table 27.8 Timing of On-Chip Peripheral Modules (2)
Condition:
XBS read
cycle
XBS write
cycle
Rev. 3.00 Mar 21, 2006 page 716 of 788
REJ09B0300-0300
* Only peripheral modules that can be used in subclock operation
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Trigger input setup time
RESO output delay time
RESO output pulse width
CS/HA0 setup time
CS/HA0 hold time
IOR pulse width
HDB delay time
HDB hold time
HIRQ delay time
CS/HA0 setup time
CS/HA0 hold time
IOW pulse width
HDB setup
time
HDB hold time
GA20 delay time
V
operating frequency, T
CC
= 2.7 V to 3.6 V, V
Item
Fast A20 gate not
used
Fast A20 gate
used
a
CC
= –20 to +75°C
B = 2.7 V to 5.5 V, V
Symbol
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
TXD
RXS
RXH
TRGS
RESD
RESOW
HAR
HRA
HRPW
HRD
HRF
HIRQ
HAW
HWA
HWPW
HDW
HWD
HGA
Min
—
100
100
50
—
132
Min
10
10
220
—
0
—
10
10
100
50
85
25
—
Condition
Condition
10 MHz
10 MHz
SS
= 0 V, = 2 MHz to maximum
Max
100
—
—
—
200
—
Max
—
—
—
200
40
200
—
—
—
—
—
—
180
Unit
ns
ns
ns
ns
ns
t
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
Test Conditions
Figure 27.24
Figure 27.25
Figure 27.26
Test Conditions
Figure 27.27