DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 75

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Type
Address
bus
Data bus
Bus control
Interrupt
signals
Symbol
A23 to
A16
A15 to A0
D15 to D8 89 to 82
D7 to D0
WAIT
RD
HWR
LWR
AS/IOS
NMI
IRQ0 to
IRQ7
FP-100B,
TFP-100B TFP-144 I/O
10, 11, 20,
21, 30, 31,
47, 48
60 to 67,
72 to 79
57, 58, 68,
69, 80, 81,
90, 91
16
22
19
25
18
7
23 to 25,
97 to 99,
34, 35
Pin No.
33, 34,
35, 37,
38, 39,
40, 41
96 to
110, 112
128 to
121
113 to
120
17
21
20
24
19
11
22 to 24,
133 to
135, 84,
85
Output Address output pins when 16-Mbyte
Output Address output pins
Input/
output
Input/
output
Input
Output When this pin is low, it indicates that the
Output When this pin is low, it indicates that the
Output When this pin is low, it indicates that the
Output When this pin is low, it indicates that
Input
Input
space is used.
Bidirectional data bus for upper byte of
16-bit data.
Bidirectional data bus for lower byte of
16-bit data.
Requests insertion of a wait state in the
bus cycle when accessing external 3-
state address space.
external address space is being read.
external address space is being written
to. The upper half of the data bus is
valid.
external address space is being written
to. The lower half of the data bus is
valid.
address output on the address bus is
valid.
Input pin for a nonmaskable interrupt
request.
These pins request a maskable
interrupt.
Rev. 3.00 Mar 21, 2006 page 19 of 788
Name and Function
Section 1 Overview
REJ09B0300-0300

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