DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 349

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 12.2 Clock Input to TCNT and Count Condition
Note:
Channel CKS2
TMR_0
TMR_1
TMR_Y
TMR_X
Common
* If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as
the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated.
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
1
CKS1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
TCR
CKS0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
ICKS1
0
1
0
1
0
1
STCR
ICKS0
0
1
0
1
0
1
Description
Disables clock input
Increments at falling edge of internal clock /8
Increments at falling edge of internal clock /2
Increments at falling edge of internal clock /64
Increments at falling edge of internal clock /32
Increments at falling edge of internal clock /1024
Increments at falling edge of internal clock /256
Increments at overflow signal from TCNT_1 *
Disables clock input
Increments at falling edge of internal clock /8
Increments at falling edge of internal clock /2
Increments at falling edge of internal clock /64
Increments at falling edge of internal clock /128
Increments at falling edge of internal clock /1024
Increments at falling edge of internal clock /2048
Increments at compare-match A from TCNT_0 *
Disables clock input
Increments at falling edge of internal clock /4
Increments at falling edge of internal clock /256
Increments at falling edge of internal clock /2048
Disables clock input
Disables clock input
Increments at falling edge of internal clock
Increments at falling edge of internal clock /2
Increments at falling edge of internal clock /4
Disables clock input
Increments at rising edge of external clock
Increments at falling edge of external clock
Increments at both rising and falling edges of
external clock.
Rev. 3.00 Mar 21, 2006 page 293 of 788
Section 12 8-Bit Timer (TMR)
REJ09B0300-0300

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