DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 496

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

Section 16 I
Bit Bit Name
4
Rev. 3.00 Mar 21, 2006 page 440 of 788
REJ09B0300-0300
ICDRE
2
C Bus Interface (IIC) (Optional)
Initial Value R/W
0
R
Description
Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
0: Indicates that the data has been already written to ICDR
1: Indicates that data has been transferred from ICDRT to
[Setting conditions]
[Clearing conditions]
Note that if the ACKE bit is set to 1 with I
enabling acknowledge bit decision, ICDRE is not set when
data transmission is completed while the acknowledge bit
is 1.
When ICDRE is set due to the condition (2) above, ICDRE
is temporarily cleared to 0 when data is written to ICDR
(ICDRT); however, since data is transferred from ICDRT to
ICDRS immediately, ICDRE is set to 1 again. Do not write
data to ICDR when TRS = 0 because the ICDRE flag value
is invalid during the time.
(ICDRT) or ICDR is initialized.
ICDRS and is being transmitted, or the start condition
has been detected or transmission has been complete,
thus allowing the next data to be written to.
When the start condition is detected from the bus line
state with I
When I
SW bit in DDCSWR is set to 1).
When data is transferred from ICDRT to ICDRS.
1. When data transmission completed while ICDRE =
2. When data is written to ICDR in transmit mode after
When data is written to ICDR (ICDRT).
When the stop condition is detected with I
or serial format.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3 to
CLR0 bits in DDCSWR.
0 (at the rise of the 9th clock pulse).
data transmission was completed while ICDRE = 1.
2
C bus mode is switched to formatless (when the
2
C bus format or serial format.
2
C bus format thus
2
C bus format