DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 33

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

15.7 IrDA Operation ................................................................................................................. 402
15.8 Interrupt Sources............................................................................................................... 405
15.9 Usage Notes ...................................................................................................................... 406
Section 16 I
16.1 Features ............................................................................................................................. 413
16.2 Input/Output Pins .............................................................................................................. 416
16.3 Register Descriptions ........................................................................................................ 417
16.4 Operation .......................................................................................................................... 442
15.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 394
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 395
15.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 398
15.6.5 Simultaneous Serial Data Transmission and Reception
15.9.1 Module Stop Mode Setting .................................................................................. 406
15.9.2 Break Detection and Processing .......................................................................... 406
15.9.3 Mark State and Break Detection .......................................................................... 406
15.9.4 Receive Error Flags and Transmit Operations
15.9.5 Relation between Writing to TDR and TDRE Flag ............................................. 406
15.9.6 Restrictions on Using DTC .................................................................................. 407
15.9.7 SCI Operations during Mode Transitions ............................................................ 407
15.9.8 Notes on Switching from SCK Pins to Port Pins ................................................. 411
16.3.1 I
16.3.2 Slave Address Register (SAR) ............................................................................. 418
16.3.3 Second Slave Address Register (SARX) ............................................................. 419
16.3.4 I
16.3.5 I
16.3.6 I
16.3.7 DDC Switch Register (DDCSWR) ...................................................................... 436
16.3.8 I
16.4.1 I
16.4.2 Initialization ......................................................................................................... 444
16.4.3 Master Transmit Operation .................................................................................. 444
16.4.4 Master Receive Operation.................................................................................... 448
16.4.5 Slave Receive Operation...................................................................................... 457
16.4.6 Slave Transmit Operation .................................................................................... 465
16.4.7 IRIC Setting Timing and SCL Control ................................................................ 468
16.4.8 Automatic Switching from Formatless Mode to I
16.4.9 Operation Using DTC .......................................................................................... 471
16.4.10 Noise Canceler ..................................................................................................... 472
(Clocked Synchronous Mode) ............................................................................. 400
(Clocked Synchronous Mode Only) .................................................................... 406
2
2
2
2
2
2
2
C Bus Data Register (ICDR) ............................................................................. 417
C Bus Mode Register (ICMR) ........................................................................... 421
C Bus Control Register (ICCR) ......................................................................... 424
C Bus Status Register (ICSR)............................................................................ 431
C Bus Extended Control Register (ICXR)......................................................... 438
C Bus Data Format ............................................................................................ 442
C Bus Interface (IIC) (Optional)
............................................................. 413
Rev. 3.00 Mar 21, 2006 page xxxi of liv
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C Bus Format ........................ 470