DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 577

• Manufacturer Part Number: DF2148BTE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148BTE20; HD64F2148BTE20

18.4.2
Table 18.4 shows host interface operations from the HIF host, and slave (this LSI) operation.
Table 18.4 Host Interface Operations from HIF Host, and Slave Operation
Note: n = 1 to 4
18.4.3
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086 * -family CPU. A regular-speed A20 gate signal can be output under
firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR
(H'FFF0).
Note: * Intel microprocessor.
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (this LSI) receives data, it normally uses an
interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1
command, software copies bit 1 of the data and outputs it at the gate A20 pin.
Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a
fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. When the DDR bit
for P81 is set to 1, the state of the P81/GA20 pin cannot be monitored by reading the DR bit for
P81. The state of the P81/GA20 pin can be monitored by reading the GA20 bit in the LPC’s
HICR2 register. The initial output from this pin will be a logic 1, which is the initial value.
Afterward, the host processor can manipulate the output from this pin by sending commands and
data. This function is available only when register IDR1 is accessed using CS1. The slave
processor (this LSI) decodes the commands input from the host processor. When an H'D1 host
Other than
CSn
CSn
CSn
CSn
1
Control States
A20 Gate
CSn
CSn
CSn
CSn
0
IOR
IOR
0
1
IOR
IOR
IOW
IOW
0
1
0
1
IOW
IOW
HA0
0
1
0
1
0
1
0
1
Operation
Setting prohibited
Setting prohibited
Data read from output data register n (ODR_n)
Status read from status register n (STR_n)
Data written to input data register n (IDR_n)
Command written to input data register n (IDR_n)
Idle state
Idle state
Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 521 of 788
REJ09B0300-0300