DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 649

IC H8S MCU FLASH 128K 100-QFP

DF2148BTE20

Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 21.2 shows the operation timing.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
State of channel 0 (AN0)
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this
time, an ADI interrupt is requested after A/D conversion ends.
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
ADDRA
ADDRB
ADDRC
ADDRD
ADST
ADF
2. Data currently being converted is ignored.
Figure 21.2 Example of A/D Converter Operation
Idle
(Scan Mode, Channels AN0 to AN2 Selected)
Idle
A/D conversion 1
Idle
Set *
1
A/D conversion 2
Transfer
Continuous A/D conversion execution
Idle
A/D conversion result 1
A/D conversion 3
Idle
Rev. 3.00 Mar 21, 2006 page 593 of 788
Idle
A/D conversion 4
A/D conversion time
A/D conversion result 2
A/D conversion result 3
Section 21 A/D Converter
A/D conversion 5
A/D conversion result 4
REJ09B0300-0300
Clear *
*
2
Idle
Idle
Idle
1
Clear *
1

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