DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 583
DF2148BTE20
Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20
HD64F2148BTE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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HIRQ Setting/Clearing Conflict: If there is conflict between a P4DR or PBODR read/write by
the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the
host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU.
P4DR or PBODR clearing is executed after completion of the read/write.
18.6
18.6.1
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol must be followed to implement necessary functions
and avoid data contention. For example, if the host and slave processors try to access the same
input or output data register simultaneously, the data will be corrupted. Interrupts can be used to
design a simple and effective protocol.
Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attempting IDR or ODR
access, signal contention will occur within the chip, and a through-current may result. This usage
must therefore be avoided.
18.6.2
XBS operation can be enabled or disabled using the module stop control register. The initial
setting is for XBS operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
Usage Notes
Note on Host Interface
Module Stop Mode Setting
Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 527 of 788
REJ09B0300-0300
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