R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 571

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
[Legend]
⎯:
• P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
SSU settings
SAE1
TPU channel 1
settings
P15DDR
NDER13
Pin function
SSU settings
SSUMS
MSS
SCKS
Pin state
The pin function is switched as shown below according to the combination of bit SAE1 in
DMABCRH of DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3
to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in
TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of PPG, bits MSS and BIDE in
SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bits SSI0S1 and SSI0S0
in PFCR5, and bit P15DDR.
Not used as the SSU pin (can be used as an I/O port).
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5. Do not set up for TPU output
4. SSI0-A output when SSI0S1 and SSI0S0 = B'00 in PFCR5. Do not set up for TPU or
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC
input when phase counting mode is set for channels 2 and 4.
or DMAC with SSCK0-A input.
DMAC with SSCK0-A output.
(1) In table
TIOCB1
output
below
(1)
⎯
⎯
⎯
0
0
SSCK
input
(2)
input
P15
1
⎯
0
(2) In table below
(1) in table below
0
TCLKC input*
0
(1)
⎯
0
output
P15
TIOCB1 input *
1
0
1
SSCK
output
(3)
2
1
output
PO13
1
1
1
(1)
⎯
0
DACK1
output
⎯
⎯
⎯
0
1
SSCK
input
(2)
1
(2) in table
SSI0-A
input*
below
1
0
(1)
Section 10 I/O Ports
⎯
0
3
⎯
⎯
⎯
Page 541 of 1392
(3) in table
1
output*
SSI0-A
below
output
SSCK
⎯
(3)
1
4