R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 326

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
(6)
In a continuous synchronous DRAM space access following a normal space access, the settings of
bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads
in different areas, for example, if the second read is a full access to continuous synchronous
DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in
figure 6.84.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Page 296 of 1392
Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal
Space Access
Figure 6.84 Example of Synchronous DRAM Full Access after External Read
Group.
Precharge-sel
DQMU, DQML
Address bus
Data bus
CKE
CAS
RAS
WE
RD
φ
External space read
T
1
NOP
T
(CAS Latency 2)
2
T
3
PALL ACTV
Column
address
T
Synchronous DRAM space read
p
address
address
Row
Row
T
r
READ
T
c1
Column address
H8S/2456, H8S/2456R, H8S/2454 Group
T
cl
NOP
REJ09B0467-0350 Rev. 3.50
T
c2
Jul 07, 2010