R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 397

MCU 256KB FLASH 48K 144-LQFP

R4F24568NVRFQV

Manufacturer Part Number
R4F24568NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of R4F24568NVRFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24568NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24568NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Set number of transfers
Set transfer source and
Single address mode
transfer destination
Read DMABCRL
Set DMABCRH
Single address
Set DMABCRL
mode setting
Set DMACR
addresses
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode Is Specified)
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address/transfer
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTE bit to 1 to enable transfer.
• Clear the FAE bit to 0 to select short address
• Set the SAE bit to 1 to select single address
• Specify enabling or disabling of internal
destination address in MAR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Clear the RPE bit to 0 to select sequential
• Specify the transfer direction with the DTDIR
• Select the activation source with bits DTF3 to
• Specify enabling or disabling of transfer end
mode.
mode.
interrupt clearing with the DTA bit.
decremented with the DTID bit.
mode.
bit.
DTF0.
interrupts with the DTIE bit.
Section 7 DMA Controller (DMAC)
Page 367 of 1392

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