R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 1160

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Synchronous Serial Communication Unit (SSU)
20.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect conflict error. The conflict
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
Page 1130 of 1392
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
CE
SCS output
φ
SCS
MSS
Internal signal for
transfer enable
CE
SCS Pin Control and Conflict Error
Figure 20.11 Conflict Error Detection Timing (After Transfer End)
Figure 20.10 Conflict Error Detection Timing (Before Transfer)
(Hi-Z)
Transfer
end
detection period
Conflict error
Data written
to SSTDR
internally clocking SCS
Maximum time for
Conflict error detection period
(Hi-Z)
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010