R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 348

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.14
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.15
6.15.1
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR =
H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered
in which the clock is also stopped for the bus controller and I/O ports. In this state, the external
bus release function is halted. To use the external bus release function in sleep mode, the ACSE
bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-
module-clocks-stopped mode is executed in the external bus released state, the transition to all-
module-clocks-stopped mode is deferred and performed until after the bus is recovered.
6.15.2
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.15.3
CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR
refresh/auto refresh request is issued.
Note: The auto refresh control function is not supported by the H8S/2456 Group and H8S/2454
Page 318 of 1392
Group.
Bus Controller Operation in Reset
Usage Notes
External Bus Release Function and All-Module-Clocks-Stopped Mode
External Bus Release Function and Software Standby
External Bus Release Function and CBR Refreshing/Auto Refreshing
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010