R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 511

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
9.2.2
MRB selects the DTC operating mode.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
4 to 0
Bit Name
CHNE
DISEL
CHNS
⎯
DTC Mode Register B (MRB)
Initial Value
Undefined
Undefined
Undefined
Undefined
R/W
⎯
⎯
⎯
⎯
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4,
Chain Transfer.
In data transfer with CHNE set to 1, determination
of the end of the specified number of transfers,
clearing of the activation source flag, and clearing
of DTCER is not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number
of data transfer ends.
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
Section 9 Data Transfer Controller (DTC)
Page 481 of 1392