R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 13

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8
6.9
6.10 Idle Cycle........................................................................................................................... 290
6.11 Write Data Buffer Function ............................................................................................... 310
6.12 Bus Release........................................................................................................................ 311
6.13 Bus Arbitration .................................................................................................................. 315
6.14 Bus Controller Operation in Reset ..................................................................................... 318
6.15 Usage Notes ....................................................................................................................... 318
6.7.10 Byte Access Control ............................................................................................. 236
6.7.11 Burst Operation..................................................................................................... 238
6.7.12 Refresh Control..................................................................................................... 244
6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 252
Synchronous DRAM Interface........................................................................................... 255
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
6.8.8
6.8.9
6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 266
6.8.11 Byte Access Control ............................................................................................. 267
6.8.12 Burst Operation..................................................................................................... 270
6.8.13 Refresh Control..................................................................................................... 274
6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 281
6.8.15 DMAC and EXDMAC Single Address Transfer Mode and
Burst ROM Interface.......................................................................................................... 287
6.9.1
6.9.2
6.9.3
6.10.1 Operation .............................................................................................................. 290
6.10.2 Pin States in Idle Cycle......................................................................................... 309
6.12.1 Operation .............................................................................................................. 311
6.12.2 Pin States in External Bus Released State ............................................................ 312
6.12.3 Transition Timing ................................................................................................. 313
6.13.1 Operation .............................................................................................................. 315
6.13.2 Bus Transfer Timing............................................................................................. 316
6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 318
6.15.2 External Bus Release Function and Software Standby ......................................... 318
Setting Continuous Synchronous DRAM Space................................................... 255
Address Multiplexing ........................................................................................... 256
Data Bus ............................................................................................................... 257
Pins Used for Synchronous DRAM Interface....................................................... 257
Synchronous DRAM Clock .................................................................................. 259
Basic Timing......................................................................................................... 259
CAS Latency Control............................................................................................ 261
Row Address Output State Control....................................................................... 263
Precharge State Count........................................................................................... 264
Synchronous DRAM Interface ............................................................................. 282
Basic Timing......................................................................................................... 287
Wait Control ......................................................................................................... 289
Write Access......................................................................................................... 289
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