D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 638

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
0
1
Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
0
1
Notes: 1. The TDRE flag in SSR is fixed at 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
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flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to
0.
2. In this state, serial transmission is started when transmit data is written to TDR and the
2. Serial reception is started in this state when a start bit is detected in asynchronous
SMR setting must be performed to decide the transfer format before setting the RE bit
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
retain their states.
mode or serial clock input is detected in synchronous mode.
to 1.
Description
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
disabled *
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
enabled
Description
Transmission disabled *
Transmission enabled *
Description
Reception disabled *
Reception enabled *
2
1
2
1
(Initial value)
(Initial value)
(Initial value)