D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 223

IC H8S/2332 MCU ROMLESS 144QFP

D12332VFC20V

Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12332VFC20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Usage Notes: When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In
the case of consecutive reads in different areas, for example, if the second access is a DRAM
access, only a T
6.34. However, in burst access in RAS down mode, the settings of these bits are enabled and an
idle cycle is inserted. The timing in this case is shown in figures 6.35 (a) and (b).
EXTAL
Address bus
RD
RAS
CAS, LCAS
Data bus
Figure 6.35 (a) Example of Idle Cycle Insertion in RAS Down Mode (ICIS1 = 1)
Address bus
RD
Data bus
p
φ
cycle is inserted, and a T
Figure 6.34 Example of DRAM Access after External Read
T
p
DRAM space read
T
r
T
T
c1
1
External read
T
T
c2
2
I
cycle is not. The timing in this case is shown in figure
T
T
3
I
External read
T
T
1
Rev.4.00 Sep. 07, 2007 Page 191 of 1210
p
DRAM space read
T
T
2
r
T
T
c1
3
Idle cycle
T
T
DRAM space read
c1
c2
REJ09B0245-0400
T
c1
T
c2

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