D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 325

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 DMA Controller
Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 at the end of a
transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU
or DTC even if DTA is set to 1.
Also, if internal DMAC activation has already been initiated when operation is forcibly
terminated, the transfer is executed but flag clearing is not performed for the selected internal
interrupt even if DTA is set to 1.
An internal interrupt request following the end of transfer or a forcible termination should be
handled by the CPU as necessary.
Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use
exclusive handling of transfer end interrupts, and perform DMABCR control bit operations
exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write a 1 to them.
Rev.4.00 Sep. 07, 2007 Page 293 of 1210
REJ09B0245-0400