D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 16

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.6
Section 6 Bus Controller
6.1
6.2
6.3
6.4
6.5
Rev.4.00 Sep. 07, 2007 Page xiv of xxx
DTC and DMAC Activation by Interrupt ......................................................................... 125
5.6.1
5.6.2
5.6.3
Overview........................................................................................................................... 129
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 134
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Overview of Bus Control .................................................................................................. 149
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Basic Bus Interface ........................................................................................................... 154
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
DRAM Interface ............................................................................................................... 167
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
Overview.............................................................................................................. 125
Block Diagram..................................................................................................... 126
Operation ............................................................................................................. 127
Features................................................................................................................ 129
Block Diagram..................................................................................................... 131
Pin Configuration................................................................................................. 132
Register Configuration......................................................................................... 133
Bus Width Control Register (ABWCR)............................................................... 134
Access State Control Register (ASTCR) ............................................................. 135
Wait Control Registers H and L (WCRH, WCRL).............................................. 135
Bus Control Register H (BCRH) ......................................................................... 140
Bus Control Register L (BCRL) .......................................................................... 142
Memory Control Register (MCR)........................................................................ 144
DRAM Control Register (DRAMCR) ................................................................. 146
Refresh Timer Counter (RTCNT)........................................................................ 148
Refresh Time Control Register (RTCOR) ........................................................... 148
Area Partitioning.................................................................................................. 149
Bus Specifications................................................................................................ 150
Memory Interfaces ............................................................................................... 151
Advanced Mode ................................................................................................... 152
Chip Select Signals .............................................................................................. 153
Overview.............................................................................................................. 154
Data Size and Data Alignment............................................................................. 154
Valid Strobes........................................................................................................ 156
Basic Timing........................................................................................................ 157
Wait Control ........................................................................................................ 165
Overview.............................................................................................................. 167
Setting DRAM Space........................................................................................... 167
Address Multiplexing........................................................................................... 168
Data Bus............................................................................................................... 169
Pins Used for DRAM Interface............................................................................ 169
Basic Timing........................................................................................................ 170
................................................................................................... 129