D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 540
D12332VFC20V
Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12332VFC20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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10.5
10.5.1
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 10.13 lists the TPU interrupt sources.
Rev.4.00 Sep. 07, 2007 Page 508 of 1210
REJ09B0245-0400
TCLKA
TCLKB
Interrupts
Interrupt Sources and Priorities
Figure 10.33 Phase Counting Mode Application Example
detection
circuit
Edge
TGR0A (speed control period)
TGR0B (pulse width capture)
TGR0D (buffer operation)
(position period capture)
(position control period)
(speed period capture)
TGR1A
TGR1B
TGR0C
TCNT1
TCNT0
Channel 1
Channel 0
+
–
+
–
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