MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 82
![IC MCU 16K FLASH 8MHZ SPI 42SDIP](/photos/12/38/123871/mc908gt16cbe_sml.jpg)
MC908GT16CBE
Manufacturer Part Number
MC908GT16CBE
Description
IC MCU 16K FLASH 8MHZ SPI 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GT8CFBE.pdf
(292 pages)
Specifications of MC908GT16CBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
34
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
42SPDIP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Internal Clock Generator (ICG) Module)
7.3.2.3 Frequency Comparator
The frequency comparator effectively compares the low-frequency base clock (IBASE) to a nominal
frequency, f
capacitor with a current reference for a period dependent on IBASE. This voltage is compared to a voltage
reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these
outputs on the capacitor size, current reference, and voltage reference causes up to ±25 percent error in
f
7.3.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock
(ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage
control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG
registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the
low-frequency base clock’s period, as shown in
operating at a V
maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and
$F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering
from this condition requires subtracting (increasing frequency) in the normal fashion until the value is
again below $9FF. (If the desired value is $9xx, the value may settle at $Axx through $Fxx. This is an
acceptable operating condition.) If the error is less than ±5 percent, the internal clock generator’s filter
stable indicator (FICGS) is set, indicating relative frequency accuracy to the clock monitor.
82
NOM
1. x = Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
Frequency Error of IBASE
carries or borrows.
.
Compared to f
IBASE < 0.85 f
0.85 f
IBASE < 0.95 f
0.95 f
IBASE < 1.05 f
1.05 f
IBASE < 1.15 f
1.15 f
IBASE < f
f
NOM
NOM
NOM
NOM
NOM
NOM
< IBASE
< IBASE
< IBASE
< IBASE
< IBASE
. First, the frequency comparator converts IBASE to a voltage by charging a known
DD
NOM
NOM
NOM
NOM
NOM
NOM
level which is out of specification, the DLF may attempt to use a value above the
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Table 7-1. Correction Sizes from DLF to DCO
DDVI[3:0]:DSTG[7:0]
+32 (+$020)
–32 (–$020)
Correction
–8 (–$008)
–1 (–$001)
+1 (+$001)
+8 (+$008)
Table
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
DDIV[3:0]:DSTG[7:0]
7-1. In some extreme error conditions, such as
Current to New
$xFF to $xDF
$xFF to $xFE
$xFE to $xFF
$xDF to $xFF
$xFF to $xF7
$xF7 to $xFF
$x20 to $x00
$x08 to $x00
$x01 to $x00
$x00 to $x01
$x00 to $x08
$x00 to $x20
(1)
+0.0625/30.9375
–0.0625/17.0625
–0.0625/31
+0.0625/17
–0.5/17.5
+0.5/30.5
Relative Correction
–0.5/31
+0.5/17
–2/31
+2/29
+2/17
–2/19
Freescale Semiconductor
in DCO
+0.202%
–6.45%
–10.5%
–1.61%
–2.86%
–0.202%
–0.366%
+0.368%
+1.64%
+2.94%
+6.90%
+11.8%
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