MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 186
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MC908GT16CBE
Manufacturer Part Number
MC908GT16CBE
Description
IC MCU 16K FLASH 8MHZ SPI 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GT8CFBE.pdf
(292 pages)
Specifications of MC908GT16CBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
34
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
42SPDIP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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System Integration Module (SIM)
15.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
15.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See
186
•
•
•
INTERRUPT
I BIT
INTERRUPT
R/W
I BIT
IDB
R/W
IAB
IDB
IAB
MODULE
MODULE
Interrupts:
–
–
Reset
Break interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
DUMMY
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
DUMMY
Figure 15-9
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 15-9. Interrupt Recovery Timing
Figure 15-8
SP – 3
shows interrupt recovery timing.
SP – 1
A
SP – 2
SP – 2
.
Interrupt Entry Timing
X
X
Figure
SP – 1
SP – 3
PC – 1 [7:0] PC – 1 [15:8] OPCODE
15-10.
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
PC + 1
VECT L
OPERAND
V DATA L
Figure 15-8
START ADDR
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