MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 180

• Manufacturer Part Number: MC908GT16CBE
• Description: IC MCU 16K FLASH 8MHZ SPI 42SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GT16CBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 36
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Controller Family/series: HC08
• No. Of I/o's: 34
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GT
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 30
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Package: 42SPDIP
• Family Name: HC08
• Maximum Speed: 8 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
180
Note: Writing a 0 clears SBSW.
Addr.
$FE00
$FE01
$FE02
PIN LOGIC
RESET
SIM Break Status Register
SIM Reset Status Register
SIM Upper Byte Address
Register Name
Register (SUBAR)
See page 193.
See page 194.
V
DD
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
INTERNAL
PULLUP
DEVICE
(SRSR)
(SBSR)
Reset:
Reset:
SIM RESET STATUS REGISTER
Read:
Read:
Read:
Write:
Write:
Write:
POR:
RESET PIN CONTROL
Figure 15-2. SIM I/O Register Summary
POR CONTROL
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
CLOCK
Figure 15-1. SIM Block Diagram
Bit 7
POR
R
R
0
1
PIN
R
R
6
0
0
CLOCK GENERATORS
RESET
COUNTER
SIM
÷ 2
COP
5
R
R
0
0
CONTROL
MASTER
RESET
ILOP
4
R
R
0
0
ILAD
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO ICG)
CGMXCLK (FROM ICG)
CGMOUT (FROM ICG)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
FORCED MONITOR MODE ENTRY
3
R
R
0
0
MODRST
2
R
R
0
0
Freescale Semiconductor
SBSW
NOTE
LVI
1
R
0
0
Bit 0
R
R
0
0
0