MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 60
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MC908GT16CBE
Manufacturer Part Number
MC908GT16CBE
Description
IC MCU 16K FLASH 8MHZ SPI 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GT8CFBE.pdf
(292 pages)
Specifications of MC908GT16CBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
34
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
42SPDIP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Configuration Register (CONFIG)
LVIPWRD — LVI Power Disable Bit
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
SSREC — Short Stop Recovery Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
60
LVIPWRD disables the LVI module. See
LVI5OR3 selects the voltage operating mode of the LVI module. See
(LVI)
Electrical Specifications
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
The short stop recovery delay can be enabled when using the internal oscillator, a crystal, or a ceramic
resonator and the OSCENINSTOP bit is set. The short stop recovery delay can be enabled when an
external oscillator is used, regardless of the OSCENINSTOP setting.
The short stop recovery delay must be disabled (SSREC = 0) when the OSCENINSTOP bit is cleared.
STOP enables the STOP instruction.
COPD disables the COP module. See
1 = LVI module power disabled
0 = LVI module power enabled
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
The voltage mode selected for the LVI should match the operating V
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
Exiting stop mode by an LVI reset will result in the long stop recovery.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
for the LVI’s voltage trip points for each of the modes.
Chapter 5 Computer Operating Properly (COP)
Chapter 10 Low-Voltage Inhibit
NOTE
NOTE
Chapter 10 Low-Voltage Inhibit
(LVI).
DD
. See
Freescale Semiconductor
Chapter 20
Module.
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