R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 657
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 620 of 802
Figure 28.4
Timer RA
Timer RA
Hardware LIN Read the Synch Break detection flag
Timer RA
Timer RA
UART0 Communication via UART0
UART0 Communication via UART0
TE bit in U0C1 register
U0TB register
U0TB register
Header Field Transmission Flowchart Example (2)
Read the count status flag
Set the timer to stop counting
Read the count status flag
Set the timer to start counting
TSTART bit in TRACR register
TCSTF flag in TRACR register
TSTART bit in TRACR register
TCSTF flag in TRACR register
SBDCT flag in LINST register
SBDCT = 1?
TCSTF = 1?
TCSTF = 0?
YES
YES
YES
Oct 30, 2009
A
0055h
ID field
1
NO
NO
NO
1
0
A Synch Break for timer RA is
generated.
After writing 1 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 1
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
A timer RA interrupt can be used to
end Synch Break generation.
One or two cycles of the CPU clock
are required after Synch Break
generation ends before the SBDCT
flag is set to 1.
After a Synch Break for timer RA is
generated, set the timer to stop
counting.
After writing 0 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 0
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA stops counting before the TCSTF
flag is set to 0.
The Synch Field is transmitted.
The ID field is transmitted.
28. Hardware LIN
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