R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 618
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 581 of 802
27.2
27.2.1
Notes:
27.2.2
1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I
2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h
3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).
4. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h
5. When the MSTTRG bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0170h
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0008h
Address 018Ch
0193h to 019Dh) is disabled.
to 015Fh) is disabled.
to 0133h) is disabled.
to 017Fh) is disabled.
Symbol
Symbol
Registers
MSTTRG Timer RG standby bit
MSTTRD Timer RD standby bit
MSTTRC Timer RC standby bit
Symbol
MSTIIC SSU, I
Symbol
IICSEL
Bit
Bit
Module Standby Control Register (MSTCR)
SSU/IIC Pin Select Register (SSUIICSR)
—
—
—
—
—
—
—
—
—
—
—
b7
b7
—
—
0
0
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
SSU/I
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
MSTTRG MSTTRC MSTTRD MSTIIC
2
2
C bus standby bit
C bus switch bit
b6
b6
—
0
0
Oct 30, 2009
Bit Name
Bit Name
b5
b5
—
0
0
b4
b4
—
0
0
0: Active
1: Standby
0: Active
1: Standby
0: Active
1: Standby
0: Active
1: Standby
0: SSU function selected
1: I
b3
b3
—
0
0
2
C bus function selected
(1)
(2, 3)
(4)
(5)
b2
b2
—
—
0
0
2
C bus associated registers (addresses
Function
Function
b1
b1
—
—
0
0
IICSEL
b0
b0
—
0
0
27. I
2
C bus Interface
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
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