R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 168
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number
Manufacturer
Quantity
Price
- Current page: 168 of 864
- Download datasheet (16Mb)
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 131 of 802
9.3
Table 9.2
—: Indicates that either 0 or 1 can be set.
High-speed
clock mode
Low-speed
clock mode
Low-speed
on-chip
oscillator
mode
Table 9.2 lists the Clock Selection in Standard Operating Mode.
In standard operating mode, the CPU and peripheral function clocks are supplied to operate the CPU and the
peripheral functions. Power control is enabled by controlling the CPU clock frequency. The higher the CPU clock
frequency, the more processing power increases. The lower the CPU clock frequency, the more power
consumption decreases. If unnecessary oscillator circuits stop, power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating and
stable. Allow sufficient wait time in a program until oscillation stabilizes before switching the clock.
Standard Operating Mode
Modes
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Clock Selection in Standard Operating Mode
OCD Register
OCD2
Oct 30, 2009
—
—
—
—
—
—
0
0
0
0
0
1
1
1
1
CM17
—
—
—
0
0
1
1
0
0
1
1
0
0
1
1
CM16
CM1 Register
—
—
—
0
1
0
1
0
1
0
1
0
1
0
1
CM14
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
CM13
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
CM07
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
CM06
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
CM0 Register
CM05
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
—
—
—
—
—
—
—
—
—
—
9. Power Control
CM04
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
—
—
—
—
—
—
—
—
—
—
CM03
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
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