R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 652
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 615 of 802
28. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
28.1
Figure 28.1
RXD0 pin
TXD0 pin
The hardware LIN has the features listed below.
Figure 28.1 shows the Hardware LIN Block Diagram.
Master mode
•
•
Slave mode
•
•
•
•
Synch Break generation
Bus collision detection
Synch Break detection
Synch Field measurement
Control function for Synch Break and Synch Field signal inputs to UART0
Bus collision detection
Introduction
Note:
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
1. The wake-up function is detected using INT1.
LSTART bit
Hardware LIN
Hardware LIN Block Diagram
LINE bit
SBE bit
RXD0 input
Oct 30, 2009
control
circuit
Synch Field
control
circuit
TIOSEL = 0
TIOSEL = 1
Bus collision
detection
circuit
MST bit
Bits BCIE, SBIE,
RXD data
and SFIE
Interrupt
control
circuit
Timer RA output pulse
UART0 transfer clock
UART0 TXD data
UART0 TE bit
underflow signal
Timer RA
Timer RA
UART0
28. Hardware LIN
Timer RA
interrupt
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