R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 607
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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- Download datasheet (16Mb)
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 570 of 802
26.5
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and
a chip select line is used for communication. This mode includes bidirectional mode in which the data input line
and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the
BIDE bit in the SSMR2 register. For details, refer to 26.3.2.1 Association between Data I/O Pins and SS Shift
Register. In this mode, the clock polarity, phase, and data settings are performed by using bits CPOS and CPHS in
the SSMR register. For details, refer to 26.3.1.1 Association between Transfer Clock Polarity, Phase, and Data.
When this MCU is set as the master device, the chip select line controls output. When the synchronous serial
communication unit is set as a slave device, the chip select line controls input. When it is set as the master device,
the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the
CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as
input by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed
MSB first.
Operation in 4-Wire Bus Communication Mode
Oct 30, 2009
26. Synchronous Serial Communication Unit (SSU)
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