R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 597
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 560 of 802
Figure 26.3
26.3.2
• SSUMS = 0 (clock synchronous communication mode)
• SSUMS = 1 (4-wire bus communication mode),
26.3.2.1
BIDE = 0 (standard mode), and
MSS = 0 (operation as a slave device)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB first), bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register.
When the MLS bit is set to 1 (LSB first), bit 7 in the SSTDR register is transferred to bit 0 in the SSTRSR
register.
The connection between the data I/O pins and the SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 26.3 shows the Association between Data I/O Pins and SSTRSR Register.
SSTRSR register
SSTRSR register
SS Shift Register (SSTRSR)
Association between Data I/O Pins and SS Shift Register
Association between Data I/O Pins and SSTRSR Register
Oct 30, 2009
SSO
SSI
SSO
SSI
• SSUMS = 1 (4-wire bus communication mode),
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 0 (standard mode), and
MSS = 1 (operation as the master device)
BIDE = 1 (bidirectional mode)
26. Synchronous Serial Communication Unit (SSU)
SSTRSR register
SSTRSR register
SSO
SSI
SSO
SSI
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