R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 484

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 451 of 723
Figure 22.6
• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits)
Transfer clock
Transfer clock
SiTIC register
SiTIC register
UiC1 register
UiC1 register
UiC0 register
UiC1 register
UiC1 register
UiC0 register
TXEPT bit in
TXEPT bit in
TE bit in
TE bit in
IR bit in
IR bit in
TI bit in
TI bit in
TXDi
TXDi
The above applies when:
The above applies when:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (one stop bit)
• UiIRS bit in UiC1 register = 1
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (two stop bits)
• UiIRS bit in UiC1 register = 0
(interrupt request generation when transmission is completed)
(interrupt request generation when the transmit buffer is empty)
Transmit Timing in UART Mode
Data is set in UiTB register.
Start
Data transfer from UiTB register to
UARTi transmit register
Start
Data is set in UiTB register.
Data transfer from UiTB register to
UARTi transmit register
bit
bit
ST
ST
D0
D0
D1
D1
TC
TC
D2
D2
D3
D3
Set to 0 when an interrupt request is acknowledged or by a program.
D4
D4
D5
D5
D6
D6
D7
D7 D8
Parity
bit
P
Stop
Stop
SP
bit
bit
SP SP
Stop
bit
ST
ST
D0
Set to 0 when an interrupt request is acknowledged or by a program.
D1
D0 D1
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
D2
fj: Frequency of UiBRG count source (f1, f8, f32, fC)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value in UiBRG register
i = 0 or 1
fj: Frequency of UiBRG count source (f1, f8, f32, fC)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value in UiBRG register
i = 0 or 1
D2 D3
D3
D4
22. Serial Interface (UARTi (i = 0 or 1))
D4
D5
D5
D6
D7
D6
Pulsing stops because TE bit is set to 0.
D7
P
D8
SP
SP SP
ST
D0 D1
ST
D0
D1