R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 461
![MCU 1KB FLASH 32K ROM 48-LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21346CNFP#U0
Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet
1.R5F21346CNFPU0.pdf
(759 pages)
Specifications of R5F21346CNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 428 of 723
21.3.3
21.3.4
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 011Ch
Address 011Dh
Symbol TSTART H12_H24
Symbol
H12_H24 Operating mode select bit
TRERST Timer RE reset bit
TSTART Timer RE count start bit
Symbol
COMIE
TOENA
Symbol
TCSTF
Bit
Bit
WKIE
MNIE
SEIE
HRIE
DYIE
Timer RE Control Register 1 (TRECR1) in Output Compare Mode
Timer RE Control Register 2 (TRECR2) in Output Compare Mode
INT
PM
—
—
—
b7
b7
—
0
0
Periodic interrupt triggered every
second enable bit
Periodic interrupt triggered every
minute enable bit
Periodic interrupt triggered every hour
enable bit
Periodic interrupt triggered every day
enable bit
Periodic interrupt triggered every
week enable bit
Compare match interrupt enable bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Timer RE count status flag
TREO pin output enable bit
Interrupt request timing bit
A.m./p.m. bit
b6
b6
—
0
0
Bit Name
Bit Name
COMIE
PM
b5
b5
0
0
TRERST
WKIE
b4
b4
0
0
0: Count stopped
1: Counting
0: Disable clock output
1: Enable clock output
Set to 0 in output compare mode.
When setting this bit to 0, after setting it to 1, the
following will occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
• Bits TCSTF, INT, PM, H12_H24, and TSTART in
• The 8-bit counter is set to 00h and the 4-bit
Set to 0 in output compare mode.
0: Count stops
1: Count starts
Set to 0 in output compare mode.
0: Disable compare match interrupt
1: Enable compare match interrupt
DYIE
INT
and TRECR2 are set to 00h.
the TRECR1 register are set to 0.
counter is set to 0h.
b3
b3
0
0
TOENA
HRIE
b2
b2
0
0
TCSTF
Function
Function
MNIE
b1
b1
0
0
SEIE
b0
b0
—
0
0
21. Timer RE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R
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