R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 23

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.
27.
25.5
25.6
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
27.1
27.2
27.3
25.4.2
25.4.3
25.5.1
25.5.2
25.5.3
25.5.4
26.2.1
26.2.2
26.2.3
26.2.4
26.2.5
26.2.6
26.2.7
26.2.8
26.2.9
26.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 542
26.2.11 Slave Address Register (SAR) .......................................................................................................... 543
26.2.12 IIC bus Shift Register (ICDRS) ........................................................................................................ 543
26.3.1
26.3.2
26.3.3
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.5.1
26.5.2
26.5.3
27.3.1
27.3.2
I
Hardware LIN .............................................................................................................................. 569
2
C bus Interface ......................................................................................................................... 532
Operation in 4-Wire Bus Communication Mode .................................................................................. 524
Notes on Synchronous Serial Communication Unit .............................................................................. 531
Overview ............................................................................................................................................... 532
Registers ................................................................................................................................................ 535
Common Items for Multiple Modes ...................................................................................................... 544
I
Clock Synchronous Serial Mode ........................................................................................................... 559
Examples of Register Setting ................................................................................................................ 562
Noise Canceller ..................................................................................................................................... 566
Bit Synchronization Circuit ................................................................................................................... 567
Notes on I
Overview ............................................................................................................................................... 569
Input/Output Pins .................................................................................................................................. 570
Registers ................................................................................................................................................ 571
2
C bus Interface Mode ......................................................................................................................... 548
Data Transmission ............................................................................................................................ 518
Data Reception .................................................................................................................................. 520
Initialization in 4-Wire Bus Communication Mode ......................................................................... 525
Data Transmission ............................................................................................................................ 526
Data Reception .................................................................................................................................. 528
SCS Pin Control and Arbitration ...................................................................................................... 530
Module Standby Control Register (MSTCR) ................................................................................... 535
SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 535
I/O Function Pin Select Register (PINSR) ....................................................................................... 536
IIC bus Transmit Data Register (ICDRT) ......................................................................................... 537
IIC bus Receive Data Register (ICDRR) .......................................................................................... 537
IIC bus Control Register 1 (ICCR1) ................................................................................................. 538
IIC bus Control Register 2 (ICCR2) ................................................................................................. 539
IIC bus Mode Register (ICMR) ........................................................................................................ 540
IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 541
Transfer Clock .................................................................................................................................. 544
SDA Pin Digital Delay Selection ...................................................................................................... 546
Interrupt Requests ............................................................................................................................. 547
I2C bus Format ................................................................................................................................. 548
Master Transmit Operation ............................................................................................................... 549
Master Receive Operation ................................................................................................................ 551
Slave Transmit Operation ................................................................................................................. 554
Slave Receive Operation ................................................................................................................... 557
Clock Synchronous Serial Format .................................................................................................... 559
Transmit Operation ........................................................................................................................... 560
Receive Operation ............................................................................................................................. 561
LIN Control Register 2 (LINCR2) .................................................................................................... 571
LIN Control Register (LINCR) ......................................................................................................... 572
2
C bus Interface .................................................................................................................... 568
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