R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 193

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 160 of 723
Figure 11.5
11.3.7
Address
m+1
m−4
m−3
m−2
m−1
m
Stack state before interrupt request acknowledgement
MSB
In the interrupt sequence, the FLG register and PC are saved on the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved on the stack, the 16 low-order bits in the PC are saved.
Figure 11.5 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers should be saved by a program at the beginning of the interrupt routine. The
PUSHM instruction can save several registers in the register bank being currently used
instruction.
Note:
Previous stack contents
Previous stack contents
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Saving Registers
Stack
Stack State Before and After Acknowledgement of Interrupt Request
Note:
1.When an INT instruction for software numbers 32 to 63 has been executed,
this SP is indicated by the U flag. Otherwise it is ISP.
LSB
[SP]
SP value before
interrupt request
acknowledgement
(1)
Address
m−4
m−3
m−2
m−1
m+1
m
Stack state after interrupt request acknowledgement
MSB
Previous stack contents
Previous stack contents
FLGH
FLGL
PCM
PCL
Stack
PCH
LSB
PCL
PCM
PCH
FLGL
FLGH
[SP]
New SP value
: 8 low-order bits of PC
: 8 middle-order bits of PC
: 4 high-order bits of PC
: 8 low-order bits of FLG
: 4 high-order bits of FLG
(1)
(1)
with a single
11. Interrupts

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