R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 477

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 444 of 723
Figure 22.3
• Transmit Timing Example (Internal Clock Selected)
• Receive Timing Example (External Clock Selected)
SiTIC register
Transfer clock
UiC1 register
UiC0 register
UiC1 register
SiRIC register
UiC1 register
TXEPT bit in
The above applies when:
UiC1 register
UiC1 register
UiC1 register
The above applies when:
The following should be met when “H” is applied to the CLKi pin before receiving data:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and
• UiIRS bit in UiC1 register = 0
fEXT: Frequency of external clock
i = 0 or 1
receive data input at the rising edge of the transfer clock)
(interrupt request generation when the transmit buffer is empty)
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and
• TE bit in UiC1 register = 1 (transmission enabled)
• RE bit in UiC1 register = 1 (reception enabled)
• Dummy data is written to UiTB register
RE bit in
TE bit in
receive data input at the rising edge of the transfer clock)
TE bit in
IR bit in
RI bit in
TI bit in
TI bit in
IR bit in
TXDi
CLKi
CLKi
RXDi
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in UiTB register.
Dummy data is set in UiTB register.
Data transfer from UARTi receive register
Data transfer from UiTB register to UARTi transmit register
Data transfer from UiTB register to UARTi transmit register
D0
D0
D1
D1
D2 D3
D2 D3
TCLK
1/fEXT
to UiRB register
D4 D5
D4 D5
TC
Receive data taken in
D6 D7
D6
Set to 0 by an interrupt request acknowledgement or by a program.
D7
D0 D1
D0 D1
Set to 0 when an interrupt request is acknowledged or by a program.
D2 D3
D2
Data read from UiRB register
D3
D4 D5
D4 D5
D6
TC = TCLK = 2(n+1)/fi
D7
fi: Frequency of UiBRG count source (f1, f8, f32, fC)
n: Setting value in UiBRG register
Pulsing stops because TE bit is set to 0.
22. Serial Interface (UARTi (i = 0 or 1))
D0 D1
D2 D3
D4 D5
D6
D7