S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 511

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.6
Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.
The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to
generate interrupt requests.
The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.
14.5
The reset state of each individual bit is listed within
which details the registers and their bit fields.
14.6
This section describes interrupts originated by the TIM16B8CV2 block.
generated by the TIM16B8CV2 to communicate with the MCU.
The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
Freescale Semiconductor
1
Chip Dependent.
Interrupt
C[7:0]F
PAOVF
PAOVI
TOF
Resets
Interrupts
Gated Time Accumulation Mode
The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
Offset
—
—
—
—
1
Vector
—
—
—
—
MC9S12HY/HA-Family Reference Manual Rev. 1.04
1
Table 14-25. TIM16B8CV1 Interrupts
Priority
—
—
—
—
1
Timer Channel 7–0
Pulse Accumulator
Pulse Accumulator
Timer Overflow
NOTE
NOTE
Section 14.3, “Memory Map and Register Definition”
Overflow
Source
Input
Active high pulse accumulator input interrupt
Timer Module (TIM16B8CV2) Block Description
Active high timer channel interrupts 7–0
Pulse accumulator overflow interrupt
Table 14-25
Timer Overflow interrupt
Description
lists the interrupts
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