S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 103

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.49
2.3.50
Freescale Semiconductor
Function
Address 0x0271
Address 0x0272
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
PT1AD
Read: Always reads 0x00
Write: Unimplemented
Altern.
Field
Reset
Reset
7-0
W
W
R
R
Port AD general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
PT1AD7
KWAD7
Port AD Data Register (PT1AD)
PIM Reserved Register
AN7
0
0
0
7
7
= Unimplemented or Reserved
PT1AD6
KWAD6
AN6
0
0
0
6
6
Table 2-43. PT1AD Register Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 2-47. Port AD Data Register (PT1AD)
PT1AD5
KWAD5
Figure 2-48. PIM Reserved Register
AN5
0
0
0
5
5
PT1AD4
KWAD4
AN4
0
0
0
4
4
Description
PT1AD3
KWAD3
AN3
3
0
3
0
0
PT1AD2
KWAD2
AN2
Port Integration Module (S12HYPIMV1)
0
0
0
2
2
PT1AD1
KWAD1
Access: User read/write
AN1
0
0
0
1
1
Access: User read
PT1AD0
KWAD0
AN0
0
0
0
0
0
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