S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 191

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
6.3.2.5
Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
Freescale Semiconductor
Address: 0x0024, 0x0025
Address: 0x0023
ABCM[1:0]
Resets
Reset
Other
Field
POR
1–0
1
W
W
R
R
Currently defaults to Comparator A, Comparator B disabled
ABCM
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
—
00
01
10
11
15
X
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
Debug Trace Buffer Register (DBGTBH:DBGTBL)
0
0
7
—
14
X
= Unimplemented or Reserved
—
13
X
Table
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
0
0
6
6-10.
Figure 6-7. Debug Trace Buffer Register (DBGTB)
—
12
X
Match 0 mapped to comparator A/B outside range: Match1 disabled.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 6-6. Debug Control Register2 (DBGC2)
Match 0 mapped to comparator A/B inside range: Match1 disabled.
Table 6-9. DBGC2 Field Descriptions
—
11
X
0
0
5
Table 6-10. ABCM Encoding
—
10
X
—
X
9
0
0
4
Bit 8
—
Description
X
8
Description
Reserved
Bit 7
—
X
7
1
0
0
3
Bit 6
—
X
6
Bit 5
—
X
5
0
0
2
Bit 4
—
X
4
S12S Debug Module (S12SDBGV2)
Bit 3
—
X
3
0
1
Bit 2
—
X
2
ABCM
Bit 1
—
X
1
0
0
Bit 0
—
X
0
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