S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 259

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.20
Read: Anytime
Write: If PROT=0 (CPMUPROT register), then write anytime. Else write has no effect
Freescale Semiconductor
IRCTRIM[9:0]
TCTRIM[3:0]
0x02F8
0x02F9
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f
Reset
Reset
15-12
Field
9-0
W
W
R
R
IRC1M temperature coefficient Trim Bits
Trim bits for the Temperature Coefficient (TC) of the IRC1M frequency.
Table 7-21
Figure 7-27
TCTRIM[3:0]=0000 or 1000).
IRC1M Frequency Trim Bits — Trim bits for Internal Reference Clock
After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in a
Internal Reference Frequency f
The frequency trimming consists of two different trimming methods:
A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average.
A fine trimming controlled by the bits IRCTRIM[5:0] can be doe with frequency leaps of about 0.3% (this trimming
determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming
values).
Figure 7-26
S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)
15
F
F
7
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC
status bits.
Figure 7-24. S12CPMU IRC1M Trim High Register (CPMUIRCTRIMH)
Figure 7-25. S12CPMU IRC1M Trim Low Register (CPMUIRCTRIML)
shows the influence of the bits TCTRIM3:0] on the relationship between frequency and temperature.
shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for
shows the relationship between the trim bits and the resulting IRC1M frequency.
14
F
F
6
TCTRIM[3:0]
Table 7-20. CPMUIRCTRIMH/L Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
13
F
F
5
IRC1M_TRIM
IRC1M_TRIM
IRC1M_TRIM
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
. See device electrical characteristics for value of f
NOTE
12
F
F
4
.
.
IRCTRIM[7:0]
Description
11
F
0
0
3
10
0
0
F
2
F
F
9
1
IRCTRIM[9:8]
IRC1M_TRIM
F
F
8
0
.
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