S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 124

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port Integration Module (S12HYPIMV1)
124
DDRV
DDRV
DDRV
DDRV
DDRV
DDRV
Field
7
6
5
4
3
2
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output or enable the TIM1 channel 3 output compare function, it will force the I/O
state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output or enable the TIM1 channel 2 output compare function, it will force the I/O
state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if IIC is routing to PV and IIC is enabled, it will force the I/O state to be open drain output, also the input buffer
is enabled
Else if PWM7 is routing to PV and PWM 7 is configured as PWM channel output, it will force the I/O state to be output
Else if PWM7 is routing to PV and PWM7 is configured as PWM emergency shutdown, it will force the I/O state to
be input
Else if SPI is routing to PV and SPI is enabled, SPI will determine the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if corresponding TIM1 output compare channle is enabled, it will be force as output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state
Else if PWM6 is routing to PV, it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-70. DDRV Register Field Descriptions
Description
Freescale Semiconductor