MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 172

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MC9S08SH16MTG

Manufacturer Part Number
MC9S08SH16MTG
Description
MCU 8BIT 16K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08SH16MTG

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Core
S08
Processor Series
MC9S08Sxx
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Data Ram Size
1 KB
On-chip Adc
Yes
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
8
Height
1.05 mm
Interface Type
SCI, SPI, I2C
Length
5 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4.4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Chapter 11 Internal Clock Source (S08ICSV2)
11.1.4
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
11.1.4.1
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
11.1.4.2
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock. The BDC clock is supplied from the FLL.
11.1.4.3
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
172
Modes of Operation
FLL Engaged Interna
FLL Engaged External
FLL Bypassed Interna
RANGE
HGO
IREFS
Figure 11-2. Internal Clock Source (ICS) Block Diagram
External Reference
Clock Source
n=0-7
RDIV
Optional
/ 2
Block
n
MC9S08SH32 Series Data Sheet, Rev. 2
IREFSTEN
EREFSTEN
Reference
Internal
RDIV_CLK
TRIM
Clock
EREFS
l (FEI)
9
l (FBI)
(FEE)
PRELIMINARY
Filter
DCO
LP
FLL
ERCLKEN
IRCLKEN
9
Internal Clock Source Block
CLKS
DCOOUT
n=0-3
BDIV
/ 2
/ 2
n
ICSERCLK
ICSIRCLK
ICSOUT
ICSLCLK
ICSFFCLK
Freescale Semiconductor

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