MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 153

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MC9S08SH16MTG

Manufacturer Part Number
MC9S08SH16MTG
Description
MCU 8BIT 16K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08SH16MTG

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Core
S08
Processor Series
MC9S08Sxx
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Data Ram Size
1 KB
On-chip Adc
Yes
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
8
Height
1.05 mm
Interface Type
SCI, SPI, I2C
Length
5 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4.4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Refer to the direct-page register summary in the
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
10.3.1
10.3.2
Freescale Semiconductor
Reset
Reset
AD[7:1]
Field
7–1
W
W
R
R
IIC Address Register (IICA)
IIC Frequency Divider Register (IICF)
AD7
Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module. This field is used on
the 7-bit address scheme and the lower seven bits of the 10-bit address scheme.
0
0
7
7
MULT
= Unimplemented or Reserved
AD6
0
0
6
6
Figure 10-4. IIC Frequency Divider Register (IICF)
Figure 10-3. IIC Address Register (IICA)
MC9S08SH32 Series Data Sheet, Rev. 2
Table 10-2. IICA Field Descriptions
AD5
0
0
5
5
PRELIMINARY
memory
AD4
0
0
4
4
Description
chapter of this document for the absolute address
AD3
3
0
3
0
ICR
Chapter 10 Inter-Integrated Circuit (S08IICV2)
AD2
0
0
2
2
AD1
0
0
1
1
0
0
0
0
0
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