ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 63

• Manufacturer Part Number: ST72F324J6T6
• Description: IC MCU 8BIT 32K 44-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.8V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• For Use With: 497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2108

ST72324Bxx
9.5.1
Table 31.
I/O port implementation
The I/O port register configurations are summarized
Table 32.
Table 33.
External interrupt on selected
external event
Port A
Port B
Port C
Port D
Port E
Port F
Reset value of all I/O port registers
Address (Hex.)
Port
000Ah
000Bh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
Interrupt event
PA7:6
PA5:4
PA3
PB3
PB4, PB2:0
PC7:0
PD5:0
PE1:0
PF7:6, 4
PF2:0
Pin name
I/O port interrupt control/wakeup capability
Port configuration
I/O port register map and reset values
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
Register label
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
OR = 0
Event flag Enable Control bit Exit from Wait
Input (DDR = 0)
-
MSB
MSB
MSB
MSB
Floating
7
0
Floating interrupt
Floating interrupt
DDRx, ORx
6
0
OR = 1
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
5
0
Table
32.
4
0
Open drain
Open drain
Open drain
Open drain
Open drain
Open drain
Open drain
Open drain
Open drain
True open-drain (high sink)
OR = 0
Yes
3
0
Output (DDR = 1)
2
0
Exit from Halt
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
Push-pull
OR = 1
1
0
Yes
I/O ports
63/193
LSB
LSB
LSB
LSB
0
0