ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 54
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ST72F324J6T6
Manufacturer Part Number
ST72F324J6T6
Description
IC MCU 8BIT 32K 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F324J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
No. Of Pwm Channels
1
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.8V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2108
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324J6T6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST72F324J6T6/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Power saving modes
8.4
8.4.1
Note:
Caution:
54/193
Active-halt and Halt modes
Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-
halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR
register).
Table 26.
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see
time clock and beeper (MCC/RTC) on page 69
The MCU can exit Active-halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see
means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation
by servicing the interrupt or by fetching the reset vector which woke it up (see
When entering Active-halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active-halt mode is provided by the oscillator
interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active-halt mode while the Watchdog is active does not generate a reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
When exiting Active-halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before t
on option byte). Otherwise, the ST7 enters Halt mode for the remaining t
Figure 26. Active-halt timing overview
1. This delay occurs only if the MCU exits Active-halt mode by means of a reset.
MCCSR OIE bit
0
1
MCC/RTC low power mode selection
Table 25: Interrupt
DELAY
after the interrupt occurs (t
Halt mode
Active-halt mode
[MCCSR.OIE = 1]
Power saving mode entered when HALT instruction is executed
Run
instruction
Halt
mapping) or a reset. When exiting Active-halt mode by
Active
Halt
256 or 4096 CPU
cycle delay
interrupt
Reset
or
Section 10.2: Main clock controller with real-
for more details on the MCCSR register).
DELAY
(1)
vector
= 256 or 4096 t
Fetch
Run
CPU
DELAY
delay depending
Figure
ST72324Bxx
period.
27).