ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 104
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ST72F324J6T6
Manufacturer Part Number
ST72F324J6T6
Description
IC MCU 8BIT 32K 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F324J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
No. Of Pwm Channels
1
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.8V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2108
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324J6T6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST72F324J6T6/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
On-chip peripherals
10.4.6
Note:
Caution:
10.4.7
10.4.8
104/193
Low power modes
Table 53.
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore,
if Slave selection is configured as external (see
make sure the master drives a low level on the SS pin when the slave enters Halt mode.
Interrupts
Table 54.
1. The SPI interrupt events are connected to the same interrupt vector (see
SPI registers
SPI control register (SPICR)
SPI end of transfer event
Master mode fault event
Overrun error
SPICR
Mode
Wait
Halt
generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC
register is reset (RIM instruction).
SPIE
R/W
Interrupt event
7
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an
interrupt with Exit from Halt mode capability. The data received is subsequently read from
the SPIDR register when the software is running (interrupt vector fetching). If several data
are received before the wakeup event, then an overrun error is generated. This error can
be detected after the fetch of the interrupt routine that woke up the device.
Effect of low power modes on SPI
SPI interrupt control/wakeup capability
SPE
R/W
6
SPR2
R/W
Event flag
5
MODF
SPIF
OVR
MSTR
R/W
4
Enable control bit
Description
SPIE
Slave select management on page
CPOL
R/W
3
(1)
CPHA
Exit from Wait
R/W
Section 7:
2
Reset value: 0000 xxxx (0xh)
Yes
Interrupts). They
1
SPR[1:0]
Exit from Halt
R/W
ST72324Bxx
Yes
No
98),
0