ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 13
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ST72F324J6T6
Manufacturer Part Number
ST72F324J6T6
Description
IC MCU 8BIT 32K 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F324J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
No. Of Pwm Channels
1
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.8V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2108
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324J6T6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST72F324J6T6/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72324Bxx
Figure 49.
Figure 50.
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Figure 92.
Figure 93.
Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data clock timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Clearing the WCOL bit (Write collision flag) software sequence . . . . . . . . . . . . . . . . . . . 103
Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Bit sampling in Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
f
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Typical application with a crystal or ceramic resonator (8/16 Kbyte Flash
and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Typical application with a crystal or ceramic resonator (32 Kbyte Flash
and ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Typical f
Integrated PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Unused I/O pins configured as input(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Typical I
Typical V
Typical V
Typical V
Typical V
Typical V
Typical V
RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Two typical applications with ICCSEL/V
SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
R
Recommended C
Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
42-pin plastic dual in-line package, shrink 600-mil width . . . . . . . . . . . . . . . . . . . . . . . . . 173
32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
32-pin plastic dual in-line package, shrink 400-mil width . . . . . . . . . . . . . . . . . . . . . . . . . 175
ST72324Bxx ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
CPU
AIN
max versus V
max. vs f
OSC(RCINT)
PU
OL
OL
OH
OL
OL
OH
vs. V
at V
at V
vs. V
vs. V
at V
vs. V
ADC
DD
DD
DD
DD
DD
DD
AIN
DD
DD
with C
= 5 V (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
= 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
vs T
with V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
(standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
(high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
and R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
A
AIN
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
AIN
= V
= 0 pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
PP
pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
List of figures
13/193