ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 189
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ST72F324J6T6
Manufacturer Part Number
ST72F324J6T6
Description
IC MCU 8BIT 32K 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F324J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
No. Of Pwm Channels
1
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.8V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2108
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324J6T6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST72F324J6T6/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72324Bxx
15.2
15.2.1
15.2.2
15.3
15.3.1
15.3.2
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
1.
2.
3.
4.
8/16 Kbyte Flash devices only
39-pulse ICC entry mode
ICC mode entry using ST7 application clock (39 pulses) is not supported. External clock
mode must be used (36 pulses). Refer to the ST7 Flash Programming Reference Manual.
Negative current injection on pin PB0
Negative current injection on pin PB0 degrades the performance of the device and is not
allowed on this pin.
8/16 Kbyte ROM devices only
Readout protection with LVD
Readout protection is not supported if the LVD is enabled.
I/O Port A and F configuration
When using an external quartz crystal or ceramic resonator, a few f
be lost when the signal pattern in
device to enter test mode and return to user mode after a few clock periods. User program
execution and I/O status are not changed, only a few clock cycles are lost.
This happens with either one of the following configurations
●
●
This is detailed in
Disable interrupts
Reset and set TE (IDLE request)
Set and reset SBK (break request)
Re-enable interrupts
PA3 = 0, PF4 = 1, PF1 = 0 while PLL option is disabled and PF0 is toggling
PA3 = 0, PF4 = 1, PF1 = 0, PF0 = 1 while PLL option is enabled
Table
125.
CPU
= 8MHz and SCIBRR = 0xC9), the wrong break duration
Table 125
occurs. This is because this pattern causes the
OSC2
Known limitations
clock periods may
189/193