ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 45

• Manufacturer Part Number: ST72F324J6T6
• Description: IC MCU 8BIT 32K 44-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.8V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• For Use With: 497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2108

ST72324Bxx
7.5
7.5.1
Figure 21. Nested interrupt management
Interrupt registers
CPU CC register interrupt bits
Table 15.
Table 16.
1. TRAP and RESET events can interrupt a level 3 program.
These two bits indicate the current interrupt software priority (see
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
CPU CC
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Bit Name
5
3
R/W
7
1
I1
I0
Interrupt software priority
Software Interrupt Priority 1
Software Interrupt Priority 0
CPU CC register interrupt bits description
Interrupt software priority levels
11 / 10
R/W
Main
RIM
6
1
IT2
(1)
IT1
R/W
I1
5
Table 18: Dedicated interrupt instruction
IT4
TRAP
R/W
H
4
IT4
IT0
Function
IT3
R/W
I0
3
IT1
Level
High
Low
IT2
10
R/W
N
2
Main
Software
priority
level
Reset value: 111x 1010(xAh)
Table
I1
1
0
0
1
set).
3
3
2
1
3
3
3/0
16) and are
R/W
1
Z
I1
1 1
1 1
0 0
0 1
1 1
1 1
Interrupts
I0
I0
R/W
0
1
0
1
C
0
45/193