ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 96

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On-chip peripherals
Note:
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How to enter one pulse mode
The steps required to enter One Pulse mode are the following:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The "Wait for Overflow" in step 6 can be replaced by a forced update.
Follow the same procedure for PWM2 with the bits corresponding to PWM2.
When break is applied in one-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So,
these registers have to be initialized again when break is removed.
Figure 49. Block diagram of one pulse mode
Figure 50. One pulse mode and PWM timing diagram
LTIC pin
PWM3CSR register
Load ATR2H/ATR2L with required value.
Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3.
Set OP3 in PWM3CSR if polarity change is required.
Select CNTR2 by setting ENCNTR2 bit in ATCSR2.
Set TRAN2 bit in ATCSR2 to enable transfer.
"Wait for Overflow" by checking the OVF2 flag in ATCSR2.
Select counter clock using CK<1:0> bits in ATCSR.
Set OP_EN bit in PWM3CSR to enable one-pulse mode.
Enable PWM3 by OE3 bit of PWMCR.
Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.
f
f
counter2
counter2
CNTR2
LTIC
CNTR2
PWM2/3
LTIC
PWM2/3
Edge
Selection
OPEDGE
OVF
ATR2
000
OP_EN
DCR2/3
DCR2/3
12-bit AutoReload register 2
12-bit Active DCR2/3
OVF
12-bit Upcounter 2
ATR2
000
OP2/3
DCR2/3
DCR2/3
Generation
PWM
OVF
ST7LITE49K2
ATR2
ATR2
000
PWM2/3